Working Principles of Intel 8086 Microprocessor
Execution of instructions can be used to explain the working principles of the microprocessor. This is given below,
- The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU.
- Register IP is incremented by 1 to prepare for the next instruction fetch.
- Once inside the BIU, the instruction is passed to the queue.
- Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution.
- While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.
The BIU is programmed to fetch a new instruction whenever the queue has room for two additional bytes. There are three conditions that will cause the EU to enter a “wait” mode or BIU to suspend fetching.
- The first one occurs when the instruction requires access to a memory location. Here the BIU must suspend fetching instructions and output the address of this memory location. Then the EU will resume execution.
- The second will occur when the instruction to be executed is a “jump” instruction. In this case control is to be transferred to a new non-sequential address.
- The third one will occur during the execution of an instruction that is slow to execute.For example, the instruction AAM (ASCII Adjust for Multiplication) requires 83 clock cycles to complete. At four cycles per instruction fetch, the queue will be completely filled during the execution of this single instruction.